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idma: Streamline TCDM connection, enable multi-channel operation #238

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38adf46
hw: Generalize DMMCAST and CSR_MCAST and adapt user field transmission
colluca Sep 24, 2025
16be330
idma: Streamline TCDM connection, enable multi-channel operation
thommythomaso Dec 6, 2024
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4 changes: 2 additions & 2 deletions Bender.lock
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Expand Up @@ -10,7 +10,7 @@ packages:
revision: bd1abffc0812f8170902e5fb93142c7785c0b8c1
version: null
source:
Git: https://github.com/colluca/axi.git
Git: https://github.com/pulp-platform/axi.git
dependencies:
- common_cells
- common_verification
Expand Down Expand Up @@ -71,7 +71,7 @@ packages:
dependencies:
- common_cells
idma:
revision: 7829f71691a62c1e2e5e3230f370f222c7a83087
revision: 9e352db1b70bc87e88670e1ef359aa3fd8bad5f6
version: null
source:
Git: https://github.com/pulp-platform/iDMA.git
Expand Down
6 changes: 4 additions & 2 deletions Bender.yml
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Expand Up @@ -19,15 +19,16 @@ package:
- Matheus Cavalcante <matheusd@iis.ee.ethz.ch>

dependencies:
axi: { git: https://github.com/colluca/axi, rev: multicast }
axi: { git: https://github.com/pulp-platform/axi, rev: multicast }
axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics, version: 0.6.0 }
common_cells: { git: https://github.com/pulp-platform/common_cells, rev: snitch }
apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.2 }
FPnew: { git: https://github.com/pulp-platform/cvfpu.git, rev: pulp-v0.1.3 }
tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version: 0.2.13 }
riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg, version: 0.8.0 }
obi: { git: "https://github.com/pulp-platform/obi.git", version: 0.1.2 }
cluster_icache: { git: https://github.com/pulp-platform/cluster_icache.git, rev: 64e21ae455bbdde850c4df13bef86ea55ac42537 }
idma: { git: https://github.com/pulp-platform/iDMA.git, rev: __deploy__bebefa3__master }
idma: { git: https://github.com/pulp-platform/iDMA, rev: 9e352db1b70bc87e88670e1ef359aa3fd8bad5f6 }

export_include_dirs:
- hw/reqrsp_interface/include
Expand Down Expand Up @@ -79,6 +80,7 @@ sources:
- hw/tcdm_interface/src/tcdm_interface.sv
# Level 1
- hw/tcdm_interface/src/axi_to_tcdm.sv
- hw/tcdm_interface/src/obi_to_tcdm.sv
- hw/tcdm_interface/src/reqrsp_to_tcdm.sv
- hw/tcdm_interface/src/tcdm_mux.sv
- target: simulation
Expand Down
20 changes: 10 additions & 10 deletions hw/reqrsp_interface/include/reqrsp_interface/typedef.svh
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Expand Up @@ -8,15 +8,15 @@
`ifndef REQRSP_INTERFACE_TYPEDEF_SVH_
`define REQRSP_INTERFACE_TYPEDEF_SVH_

`define REQRSP_TYPEDEF_REQ_CHAN_T(__req_chan_t, __addr_t, __data_t, __strb_t) \
`define REQRSP_TYPEDEF_REQ_CHAN_T(__req_chan_t, __addr_t, __data_t, __strb_t, __user_t) \
typedef struct packed { \
__addr_t addr; \
__addr_t mask; \
logic write; \
reqrsp_pkg::amo_op_e amo; \
__data_t data; \
__strb_t strb; \
reqrsp_pkg::size_t size; \
__addr_t addr; \
logic write; \
reqrsp_pkg::amo_op_e amo; \
__data_t data; \
__strb_t strb; \
__user_t user; \
reqrsp_pkg::size_t size; \
} __req_chan_t;

`define REQRSP_TYPEDEF_RSP_CHAN_T(__rsp_chan_t, __data_t) \
Expand All @@ -39,8 +39,8 @@
logic q_ready; \
} __rsp_t;

`define REQRSP_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t) \
`REQRSP_TYPEDEF_REQ_CHAN_T(__name``_req_chan_t, __addr_t, __data_t, __strb_t) \
`define REQRSP_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t, __user_t) \
`REQRSP_TYPEDEF_REQ_CHAN_T(__name``_req_chan_t, __addr_t, __data_t, __strb_t, __user_t) \
`REQRSP_TYPEDEF_RSP_CHAN_T(__name``_rsp_chan_t, __data_t) \
`REQRSP_TYPEDEF_REQ_T(__name``_req_t, __name``_req_chan_t) \
`REQRSP_TYPEDEF_RSP_T(__name``_rsp_t, __name``_rsp_chan_t)
Expand Down
2 changes: 1 addition & 1 deletion hw/reqrsp_interface/src/axi_to_reqrsp.sv
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Expand Up @@ -448,7 +448,7 @@ module axi_to_reqrsp_intf #(
typedef logic [IdWidth-1:0] id_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
Expand Down
11 changes: 9 additions & 2 deletions hw/reqrsp_interface/src/reqrsp_cut.sv
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Expand Up @@ -12,6 +12,8 @@ module reqrsp_cut #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Request type.
parameter type req_t = logic,
/// Response type.
Expand All @@ -32,8 +34,9 @@ module reqrsp_cut #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

spill_register #(
.T (reqrsp_req_chan_t),
Expand Down Expand Up @@ -74,6 +77,8 @@ module reqrsp_cut_intf #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Bypass request channel.
parameter bit BypassReq = 0,
/// Bypass Response channel.
Expand All @@ -88,15 +93,17 @@ module reqrsp_cut_intf #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

reqrsp_req_t reqrsp_slv_req, reqrsp_mst_req;
reqrsp_rsp_t reqrsp_slv_rsp, reqrsp_mst_rsp;

reqrsp_cut #(
.AddrWidth (AddrWidth),
.DataWidth (DataWidth),
.UserWidth (UserWidth),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.BypassReq (BypassReq),
Expand Down
5 changes: 4 additions & 1 deletion hw/reqrsp_interface/src/reqrsp_demux.sv
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Expand Up @@ -104,6 +104,8 @@ module reqrsp_demux_intf #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Amount of outstanding responses. Determines the FIFO size.
parameter int unsigned RespDepth = 8,
// Dependent parameters, DO NOT OVERRIDE!
Expand All @@ -120,8 +122,9 @@ module reqrsp_demux_intf #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

reqrsp_req_t reqrsp_slv_req;
reqrsp_rsp_t reqrsp_slv_rsp;
Expand Down
11 changes: 9 additions & 2 deletions hw/reqrsp_interface/src/reqrsp_iso.sv
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Expand Up @@ -14,6 +14,8 @@ module reqrsp_iso #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Request type.
parameter type req_t = logic,
/// Response type.
Expand Down Expand Up @@ -43,8 +45,9 @@ module reqrsp_iso #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

isochronous_spill_register #(
.T (reqrsp_req_chan_t),
Expand Down Expand Up @@ -89,6 +92,8 @@ module reqrsp_iso_intf #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Bypass.
parameter bit BypassReq = 0,
parameter bit BypassRsp = 0
Expand All @@ -110,15 +115,17 @@ module reqrsp_iso_intf #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

reqrsp_req_t reqrsp_src_req, reqrsp_dst_req;
reqrsp_rsp_t reqrsp_src_rsp, reqrsp_dst_rsp;

reqrsp_iso #(
.AddrWidth (AddrWidth),
.DataWidth (DataWidth),
.UserWidth (UserWidth),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.BypassReq (BypassReq),
Expand Down
11 changes: 9 additions & 2 deletions hw/reqrsp_interface/src/reqrsp_mux.sv
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Expand Up @@ -14,6 +14,8 @@ module reqrsp_mux #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Request type.
parameter type req_t = logic,
/// Response type.
Expand All @@ -39,8 +41,9 @@ module reqrsp_mux #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_REQ_CHAN_T(req_chan_t, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_REQ_CHAN_T(req_chan_t, addr_t, data_t, strb_t, user_t)

localparam int unsigned LogNrPorts = cf_math_pkg::idx_width(NrPorts);

Expand Down Expand Up @@ -159,6 +162,8 @@ module reqrsp_mux_intf #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Amount of outstanding responses. Determines the FIFO size.
parameter int unsigned RespDepth = 8,
/// Cut timing paths on the request path. Incurs a cycle additional latency.
Expand All @@ -175,8 +180,9 @@ module reqrsp_mux_intf #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

reqrsp_req_t [NrPorts-1:0] reqrsp_slv_req;
reqrsp_rsp_t [NrPorts-1:0] reqrsp_slv_rsp;
Expand All @@ -188,6 +194,7 @@ module reqrsp_mux_intf #(
.NrPorts (NrPorts),
.AddrWidth (AddrWidth),
.DataWidth (DataWidth),
.UserWidth (UserWidth),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.RespDepth (RespDepth),
Expand Down
18 changes: 7 additions & 11 deletions hw/reqrsp_interface/src/reqrsp_to_axi.sv
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Expand Up @@ -48,15 +48,13 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
parameter int unsigned ID = 0,
/// Data width of bus, must be 32 or 64.
parameter int unsigned DataWidth = 32'b0,
parameter int unsigned UserWidth = 32'b0,
parameter type reqrsp_req_t = logic,
parameter type reqrsp_rsp_t = logic,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
input logic [UserWidth-1:0] user_i,
input reqrsp_req_t reqrsp_req_i,
output reqrsp_rsp_t reqrsp_rsp_o,
output axi_req_t axi_req_o,
Expand Down Expand Up @@ -175,7 +173,7 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
assign axi_req_o.ar.lock = (reqrsp_req_i.q.amo == AMOLR);
assign axi_req_o.ar.cache = axi_pkg::CACHE_MODIFIABLE;
assign axi_req_o.ar.id = $unsigned(ID);
assign axi_req_o.ar.user = user_i;
assign axi_req_o.ar.user = reqrsp_req_i.q.user;
assign axi_req_o.ar_valid = q_valid_read;
assign q_ready_read = axi_rsp_i.ar_ready;

Expand All @@ -190,11 +188,11 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
assign axi_req_o.aw.lock = (reqrsp_req_i.q.amo == AMOSC);
assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE;
assign axi_req_o.aw.id = $unsigned(ID);
assign axi_req_o.aw.user = user_i;
assign axi_req_o.aw.user = reqrsp_req_i.q.user;
assign axi_req_o.w.data = write_data;
assign axi_req_o.w.strb = reqrsp_req_i.q.strb;
assign axi_req_o.w.last = 1'b1;
assign axi_req_o.w.user = user_i;
assign axi_req_o.w.user = reqrsp_req_i.q.user;

// Both channels need to handshake (independently).
stream_fork #(
Expand Down Expand Up @@ -305,12 +303,11 @@ module reqrsp_to_axi_intf #(
parameter int unsigned AddrWidth = 32'd0,
/// AXI and REQRSP data width.
parameter int unsigned DataWidth = 32'd0,
/// AXI user width.
parameter int unsigned AxiUserWidth = 32'd0
/// AXI and REQRSP user width.
parameter int unsigned UserWidth = 32'd0
) (
input logic clk_i,
input logic rst_ni,
input logic [AxiUserWidth-1:0] user_i,
REQRSP_BUS reqrsp,
AXI_BUS axi
);
Expand All @@ -319,9 +316,9 @@ module reqrsp_to_axi_intf #(
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [AxiIdWidth-1:0] id_t;
typedef logic [AxiUserWidth-1:0] user_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
Expand All @@ -347,7 +344,6 @@ module reqrsp_to_axi_intf #(
) i_reqrsp_to_axi (
.clk_i,
.rst_ni,
.user_i,
.reqrsp_req_i (reqrsp_req),
.reqrsp_rsp_o (reqrsp_rsp),
.axi_req_o (axi_req),
Expand Down
3 changes: 1 addition & 2 deletions hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv
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Expand Up @@ -58,11 +58,10 @@ module reqrsp_to_axi_tb import reqrsp_pkg::*; #(
.AxiIdWidth (IW),
.AddrWidth (AW),
.DataWidth (DW),
.AxiUserWidth (UW)
.UserWidth (UW)
) i_reqrsp_to_axi (
.clk_i (clk),
.rst_ni (rst_n),
.user_i ('0),
.reqrsp (master),
.axi (slave)
);
Expand Down
6 changes: 4 additions & 2 deletions hw/snitch/src/riscv_instr.sv
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Expand Up @@ -327,7 +327,8 @@ package riscv_instr;
localparam logic [31:0] DMSTAT = 32'b0000101?????00000000?????0101011;
localparam logic [31:0] DMSTR = 32'b0000110??????????000000000101011;
localparam logic [31:0] DMREP = 32'b000011100000?????000000000101011;
localparam logic [31:0] DMMCAST = 32'b000100000000?????000000000101011;
localparam logic [31:0] DMUSER = 32'b0001000??????????000000000101011;
localparam logic [31:0] DMINIT = 32'b0001001??????????000?????0101011;
localparam logic [31:0] FREP_O = 32'b????????????????????????10001011;
localparam logic [31:0] IREP = 32'b?????????????????????????0111111;
localparam logic [31:0] SCFGRI = 32'b????????????00000001?????0101011;
Expand Down Expand Up @@ -1140,7 +1141,8 @@ package riscv_instr;
localparam logic [11:0] CSR_FPMODE = 12'h7c1;
localparam logic [11:0] CSR_BARRIER = 12'h7c2;
localparam logic [11:0] CSR_SC = 12'h7c3;
localparam logic [11:0] CSR_MCAST = 12'h7c4;
localparam logic [11:0] CSR_USER_LOW = 12'h7c4;
localparam logic [11:0] CSR_USER_HIGH = 12'h7c5;
localparam logic [11:0] CSR_HTIMEDELTAH = 12'h615;
localparam logic [11:0] CSR_CYCLEH = 12'hc80;
localparam logic [11:0] CSR_TIMEH = 12'hc81;
Expand Down
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