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openresty / luajit2 Public

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Add RISC-V 64 Support for LuaJIT v2.1#236

Open

infiWang wants to merge 22 commits intoopenresty:v2.1-agentzhopenresty/luajit2:v2.1-agentzhfrom

infiWang:v2.1-riscv64infiWang/luajit2:v2.1-riscv64Copy head branch name to clipboard

Conversation Commits22 (22)Checks Files changed

Open

Add RISC-V 64 Support for LuaJIT v2.1#236
infiWang wants to merge 22 commits intoopenresty:v2.1-agentzhfrom
infiWang:v2.1-riscv64

Commits

Commits on Nov 27, 2025

riscv(support): add RISC-V 64 arch base definition
infiWang
committed
riscv(dynasm): add RISC-V support
infiWang
committed
riscv(interp): add register definition
infiWang
committed
riscv(interp): add frame definition
infiWang
committed
riscv(interp): add helper macros and typedefs
infiWang
committed

Commits on Dec 1, 2025

riscv(interp): add base assembly interpreter VM
infiWang
committed
riscv(support): add target definition
infiWang
committed
riscv(ffi): add call convention and support framework
infiWang
committed
riscv(support): add extension detection
infiWang
committed
riscv(jit): add insn emitter
infiWang
committed
riscv(jit): add IR assembler
infiWang
committed
riscv(interp): add VM builder support

infiWang
and
xypron
committed
riscv(misc): add bytecode listing support
infiWang
committed
riscv(jit): add hooks in interpreter
infiWang
committed
riscv(interp): add DWARF info
infiWang
committed
riscv(jit): add GDBJIT support
infiWang
committed
riscv(support,linux): add Linux specfic icache sync codepath
infiWang
committed
riscv(support,linux): make mremap() non-moving due to VA space woes
infiWang
committed
riscv(misc): add disassmbler support
infiWang
committed
riscv(misc): add support in Makefile
infiWang
committed
riscv(support,linux): use HWPROBE for ISE detection
infiWang
committed
riscv(interp): strip excessive extended branch (^B+J)
infiWang
committed

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