Add of a Vector Interface to InterFLOP

[a-hamitouche]

Proposed Interface for enhanced backend utilization of SIMD acceleration and overhead reduction

Completed work

• Developed a vector interface designed for floating-point operations in single and double precision.
  • Implemented data processing via pointers to accommodate various vector sizes (128, 256, 512 bits).
  • Segregated targeted SIMD registers to discern instruction set usage, particularly crucial for x86 processors to mitigate performance degradation when combining legacy SSE and AVX instructions.

Encountered challenges

The majority of this work was executed using the PENE frontend, reliant on Intel Pin. Presently, Pin's runtime lacks support for quadruple precision floating-point operations, resulting in a backend crash. This crash is attributed to the utilization of FMA from the quadmath library.

To rectify this issue, the math library has been adopted in lieu of quadmath, and quadruple precision has been substituted with extended precision (80-bits).