fix(bmi270): correct interrupt pin configuration logic #567
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Description
Motivation and Context
Previously, the interrupt pin remained in a high-impedance state because the Output Enable bit (Bit 3) in INT1_IO_CTRL was not being set. Additionally, incorrect bit-shifting logic caused Open-Drain and Active-Level settings to be applied to the wrong register bits. Finally, the internal Data Ready signal was not mapped to the physical pin in the INT_MAP_DATA register, preventing the host MCU from receiving interrupts.
How has this been tested?
I tested this on an ESP32-C3 with a BMI270 sensor using I2C.
Hardware: ESP32-C3 (Revision v0.4), BMI270
Environment: ESP-IDF v5.4.3
Test Case:
Screenshots (if appropriate, e.g. schematic, board, console logs, lab pictures):
Before Fix (Interrupts not firing): The GPIO Output Enable was 0 (disabled), and no data was printed after starting the task.
After Fix (Data Streaming): The GPIO Output Enable is 1, and interrupts trigger data reads correctly.
Types of changes
Software
.github/workflows/build.ymlfile to add my new test to the automated cloud build github action.