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1. iris-recognition-ubiris-v2 iris-recognition-ubiris-v2 Public

   A robust pipeline for iris recognition under challenging conditions using the UBIRIS.v2 dataset. Features synthetic noise simulation, data augmentation, deep learning-based image enhancement, and R…

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3. Canvas-Painting-Language-Lex-Yacc Canvas-Painting-Language-Lex-Yacc Public

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4. Round-Robin-Scheduler-C-Language Round-Robin-Scheduler-C-Language Public

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5. 32-bit-RISC-V-Cpu-Design-Verilog 32-bit-RISC-V-Cpu-Design-Verilog Public

   This RISCV CPU Architecture is designed on the efficient and effective operation of all instructions. However, for simulation purposes, a processor that can work with 15 instructions has been desig…

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6. Cache-Controller-and-Branch-Prediction-Verilog Cache-Controller-and-Branch-Prediction-Verilog Public

   The main memory module implements the memory behavior with a data chunk size of 32 bytes and a 100 cycles operation delay. the cache module contains a state machine that allows 4-byte aligned read/…

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