Pinned Loading

1. riscv-alu-isa-verilog riscv-alu-isa-verilog Public

   Verilog

2. l1-cache-performance-simulator l1-cache-performance-simulator Public

   Verilog implementation of L1 cache (direct-mapped, 4-way, fully-associative) with simulation outputs

   Verilog

3. systolic-array-ai-accelerator systolic-array-ai-accelerator Public

   C++

4. wafer-defect-classification-imbalanced-cnn wafer-defect-classification-imbalanced-cnn Public

   Python

5. entropy-based-lcd-defect-detection entropy-based-lcd-defect-detection Public

   Python