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1. Assignment1_XOR Assignment1_XOR Public

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2. Assignment2_Interface Assignment2_Interface Public

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3. NASSCOM_SEMICONDUCTOR_WORKSHOP-July-4-to-13-2025 NASSCOM_SEMICONDUCTOR_WORKSHOP-July-4-to-13-2025 Public

4. SILICLUSTER_UART_TX_and_UART_RX_2025 SILICLUSTER_UART_TX_and_UART_RX_2025 Public

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5. ARM32_BIT_CPU_DESIGN ARM32_BIT_CPU_DESIGN Public

   Replicated and implemented a 32-bit ARM-style CPU in Verilog/SystemVerilog, covering full datapath, control logic, ALU, and memory integration, with functional verification through RTL simulation.

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6. APB-MEMORY-UVM-VERIFICATION APB-MEMORY-UVM-VERIFICATION Public

   APB Memory Verification using UVM with protocol checks and waveform analysis

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