[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm. #10339
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…se gemm. Signed-off-by: Yukun He <23156053+hyukn@users.noreply.github.com>
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📝 WalkthroughWalkthroughThese changes optimize kernel tactic exploration and backend selection logic. The first modifies prefetch option experimentation to target larger K values. The second conditionally enables the 'cutedsl' backend for configurations with higher tensor parallelism. Changes
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🧹 Nitpick comments (1)
tensorrt_llm/_torch/modules/linear.py (1)
2108-2111: Consider creating a defensive copy to avoid mutating shared lists.The in-place mutation of
nvfp4_allowed_backendscould affect otherLinearinstances if they share the same list object (e.g., when passed frommodel_extra_attrsor as a parameter). While the duplicate check on Line 2110 prevents adding 'cutedsl' multiple times, creating a copy before mutation would make the behavior more predictable.🔎 Suggested defensive copy pattern
+ # Make a copy to avoid mutating shared lists from model_extra_attrs or parameters + self.nvfp4_allowed_backends = list(self.nvfp4_allowed_backends) + # Add cutedsl to the allowed backends if tp size is greater than or equal to 4, # because distributed tuning can decrease the tuning time by tp_size. if self.tp_size >= 4 and 'cutedsl' not in self.nvfp4_allowed_backends: self.nvfp4_allowed_backends.append('cutedsl')Alternatively, if the mutation is intentional (to apply the configuration model-wide), document this behavior clearly in the docstring.
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tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.pytensorrt_llm/_torch/modules/linear.py
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tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.pytensorrt_llm/_torch/modules/linear.py
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tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.pytensorrt_llm/_torch/modules/linear.py
🧠 Learnings (6)
📚 Learning: 2025-12-12T10:07:31.564Z
Learnt from: lirundong
Repo: NVIDIA/TensorRT-LLM PR: 9725
File: tensorrt_llm/_torch/custom_ops/cuda_tile_custom_ops.py:110-178
Timestamp: 2025-12-12T10:07:31.564Z
Learning: In PyTorch custom operators registered with torch.library.custom_op, mutable operators that return None and specify mutates_args do not require a register_fake decorator. Mutation tracking is handled automatically without needing a FakeTensor kernel. This applies to Python custom op definitions in tensorrt_llm/_torch/custom_ops that use mutates_args and return None; verify you are not relying on register_fake in these cases.
Applied to files:
tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.
Applied to files:
tensorrt_llm/_torch/modules/linear.py
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation.
Applied to files:
tensorrt_llm/_torch/modules/linear.py
📚 Learning: 2025-09-23T15:13:48.819Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.
Applied to files:
tensorrt_llm/_torch/modules/linear.py
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device implementation, NCCL version 2.28+ requirements are handled at runtime in the nccl_device/config layer rather than with compile-time guards. This allows the allreduceOp to remain version-agnostic and delegates version compatibility validation to the appropriate lower-level components that can gracefully handle unsupported configurations.
Applied to files:
tensorrt_llm/_torch/modules/linear.py
📚 Learning: 2025-08-21T21:48:35.135Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/fusion/sm90_visitor_scatter.hpp:399-417
Timestamp: 2025-08-21T21:48:35.135Z
Learning: CUTLASS extensions in TensorRT-LLM (located under cpp/tensorrt_llm/cutlass_extensions/) are designed to integrate with and extend functionality in the external CUTLASS repository. When analyzing these extensions, their consumers and functionality wiring may exist in the CUTLASS codebase rather than within TensorRT-LLM itself.
Applied to files:
tensorrt_llm/_torch/modules/linear.py
🧬 Code graph analysis (1)
tensorrt_llm/_torch/modules/linear.py (1)
tensorrt_llm/_torch/distributed/communicator.py (1)
tp_size(64-65)
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🔇 Additional comments (1)
tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py (1)
482-484: LGTM! Prefetch pruning optimization looks good.The conditional prefetch candidate logic appropriately narrows the tactic search space for smaller K values, reducing tuning time without sacrificing performance where prefetch matters most (large K).
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