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Clock misconfiguration leading to CAN bit rate being a third of what is should be #1

@1mozolacal

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@1mozolacal

Clock misconfigure issue

As identified here http://www.electronicsworkshop.eu/SAMC21XplainedPro-CAN-Troubleshooting the samC21 can operate and a clock speed of ⅓ of the normal. This is caused by this line in the conf_clocks.h file:

# define CONF_CLOCK_OSC48M_FREQ_DIV SYSTEM_OSC48M_DIV_3

The fix proposed in the webpage is to change SYSTEM_OSC48M_DIV_3 to SYSTEM_OSC48M_DIV_1.
This causes issues for the board for unknown reasons; it fails to finish it’s configuration. Instead we will change the CAN configurations in the conf_can.h file. The documentation http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42464-SAMC21-CAN-BUS-Firmware_ApplicationNote_AT6493.pdf ; as per the documentation “48MHz / (5 + 1) = 8MHz, and each bit is (3 + 10 + 3) or 16 time quanta which is 8MHz / 16 = 500kHz.”. Now our clock because of the division by 3 is not 48MHz but rather 16MHz. Anaylsising the equation that they provided means that simply changing the NBRP value from a 5 to a 1 should remedy this issue.

**sorry for the poor formatting

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