I have some question about module 3 Interlude: Chisel Standard Library

[linuxlonelyeagle]

new Module {
    // Example circuit using a Queue
    val io = IO(new Bundle {
      val in = Flipped(Decoupled(UInt(8.W)))
      val out = Decoupled(UInt(8.W))
    })
    val queue = Queue(io.in, 2)  // 2-element queue
    io.out <> queue

• Why do we use Flipped here?
• Why Queue(io.in, 2) is used here?
  I don't quite understand why io.in is used here.
• Why is io.out <> queue used here?
  I think the most critical part is that I have no way to imagine the corresponding hardware structure.If anyone can help me, I would appreciate it.Thanks!